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1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2003, 2004, 2007, 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. flexible double ended voltage and current mode pwm controllers isl6740, ISL6741 the isl6740, ISL6741 family of adjustable frequency, low power, pulse width modulating (pwm) voltage mode (isl6740) and current mode (ISL6741) controllers is designed for a wide range of power conversion applic ations using half-bridge, full bridge, and push-pull configurations. these controllers provide an extremely flexible oscillator that allows precise control of frequency, duty cycle, and deadtime. this advanced bicmos design fe atures low operating current, adjustable switching frequency up to 1mhz, adjustable soft- start, internal and external ov er-temperature protection, fault annunciation, and a bidirectional sync signal that allows the oscillator to be locked to paralleled units or to an external clock for noise sensitive applications. features ? precision duty cycle and deadtime control ? 95a start-up current ? adjustable delayed overcurrent shutdown and re-start (isl6740) ? adjustable short circuit shutdown and re-start ? adjustable oscillator frequency up to 2mhz ? bidirectional synchronization ? inhibit signal ? internal over-temperature protection ? system over-temperature protection using a thermistor or sensor ? adjustable soft-start ? adjustable input undervoltage lockout ? fault signal ? tight tolerance voltage reference over line, load, and temperature ? pb-free available (rohs compliant) applications ? telecom and datacom power ? wireless base station power ? file server power ? industrial power systems ? dc transformers and buss regulators pin configuration isl6740, ISL6741 (16 ld soic, 16 ld tssop) top view ordering information part number (notes 2, 3) part marking temp. range (c) package pkg. dwg. # isl6740ibz (note 1) 6740ibz -40 to +105 16 ld soic (pb-free) m16.15 isl6740ivz (note 1) isl67 40ivz -40 to +105 16 ld tssop (pb-free) m16.173 ISL6741ib ISL6741ib -40 to +105 16 ld soic m16.15 ISL6741ibz (note 1) 6741ibz -40 to +105 16 ld soic (pb-free) m16.15 ISL6741ivz (note 1) isl67 41ivz -40 to +105 16 ld tssop (pb-free) m16.173 notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ special pb- free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb -free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb- free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl6740 , ISL6741 . for more information on msl please see techbrief tb363 . isl674x x = control mode 0voltage mode 1current mode outa gnd scset c t sync cs v error outb v ref v dd r td r tc ots fault 1 2 3 4 5 6 7 16 15 14 13 12 11 10 8 9 uv ss december 2, 2011 fn9111.6
isl6740, ISL6741 2 fn9111.6 december 2, 2011 functional block diagram isl6740 vref 5.00 v 1% gnd vdd vref sync enable uv scset rtd 1.00v ct irtd ext. sync clk inhibit/vin uv inhibit fl outa outb 0.4 cs verror 0.5 ss pwm comparator n_sync out 0.6v 0.4 oc detect v ref ss pwm latch reset dominant on oc latch 4.5v 4.25v 0.27v ss low fault latch set dominant fl v ref vref uv 4.65v ss clamp ots faul t pwm toggle vref/2 inhibit ss done ss low sc latch oc s/d oc s/d sc s/d sc s/d ss hi 300k 100 4.5k bi-directional synchronization sync in oscillator short circuit detection + - + - + - + - + - rtc irtc + - - s r q q s r q q s r q q s r q q ss done + - + - 70a 15a + - bg + - bg t q q q q 50s retriggerable one shot + - internal ot shutdown +130c to +150c
isl6740, ISL6741 3 fn9111.6 december 2, 2011 functional block diagram (continued) gnd vdd vref sync enable uv scset rtd 1.00 v ct irtd ext. sync clk inhibit/vin uv inhibit fl outa outb 80mv 0.25 cs verror 0.2 ss pwm comparator n_sync out 0.6v oc detect v ref ss pwm latch reset dominant on 4.5v 0.27v ss low fault latch set dominant fl v ref vref uv 4.65v ss clamp ots fault pwm toggle vref/2 inhibit ss done sc latch sc s/d sc s/d 300k 100 4.5k sync in oscillator short circuit detection + - + - + - + - rtc irtc + - + - - s r q q s r q q s r q q ss done + - + - 70a 15a + - bg + - bg t q q + - ISL6741 bi-directional synchronization internal ot shutdown +130c to +150c vref 5.00 v 1%
isl6740, ISL6741 4 fn9111.6 december 2, 2011 typical application (isl6740) - 48v input dc transformer, 12v @ 8a output (isl6740eval1) vin+ vin- +12v rtn hip2101 vdd hb ho hs lo li hi vss v ref cr2 r6 r14 rt1 r19 r13 r15 c16 c17 c10 c18 c8 r18 c6 r17 r2 r7 q5 c4 c5 ql qh c2 c3 c1 r1 r5 l1 u1 u3 cr1 l2 t1 t2 r12 d1 qr1 qr2 l3 c13 r10 c14 r11 r3 c15 c9 qr4 qr3 r9 r8 c12 c11 cr3 tp6 tp2 tp4 tp5 tp1 sp1 c7 isl6740 gnd rtd v dd vref sync uv scset rtc ct cs verror fault ots ss outb outa u1
isl6740, ISL6741 5 fn9111.6 december 2, 2011 typical application (isl6740) - 36v to 75v inpu t, regulated 12v @ 8a output (isl6740eval2z) vin+ vin- +12v rtn hip2101 vdd hb ho hs lo li hi vss v ref cr2 r6 r14 rt1 r19 r13 r15 c16 c17 c10 c18 c8 r18 c6 r17 r2 r7 q5 c4 c5 ql qh c2 c3 c1 r1 r5 l1 36v to 75v u1 u3 cr1 l2 t1 t2 r12 d1 qr1 qr2 l3 c13 r10 c14 r11 r3 c15 c9 qr4 qr3 r9 r8 c12 c11 cr3 tp6 tp2 tp4 tp5 tp1 sp1 c7 r23 r24 r21 c20 c19 u2 u4 + 12v r19 r20 isl6740 gnd rtd vdd vref sync uv scset rtc ct cs verror fault ots ss outb outa r4 c22 c21 cr5 r26 + d2 r25 cr6 r27 cr4
isl6740, ISL6741 6 fn9111.6 december 2, 2011 typical application (ISL6741) - 48v to 5v push-pull dc/dc converter +48v vin- +5v rtn r10 r9 c5 c6 c9 r7 c2 r6 r4 r5 q3 q1 q2 c1 l1 t1 vr1 qr1 qr2 c3 r15 r17 r16 c8 c7 u2 u4 + 5v r13 r14 ISL6741 gnd rtd vdd vref sync uv scset rtc ct cs verror fault ots ss outb outa t3 outa outb u5 r19 r20 cr4 cr3 + 5v r18 u3 cr1 cr2 el7242 + sync r2 r3 r1 r8 c4 r11 r12 rt1 r21
isl6740, ISL6741 7 fn9111.6 december 2, 2011 absolute maximum ratings (note 6) thermal information supply voltage, v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +20.0v outa, outb, signal pins . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to v ref vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .gnd - 0.3v to 6.0v peak gate current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5a esd classification human body model (per mil-std-883 method 3015.7) . . . . . . . . 1500v charged device model (per eos/es d ds5.3, 4/14/93). . . . . . . . 1000v operating conditions temperature range isl6740ix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +105c ISL6741ix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +105c supply voltage range (typical). . . . . . . . . . . . . . . . . . . . . . . . 9vdc - 16vdc thermal resistance (typical) ja (c/w) jc (c/w) 16 lead soic (notes 4, 5) . . . . . . . . . . . . . . 74 33 16 lead tssop (notes 4, 5) . . . . . . . . . . . . 98 30 maximum junction temperature . . . . . . . . . . . . . . . . . . . .-55c to +150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 . 5. for jc , the ?case temp? location is taken at the package top center. 6. all voltages are with respect to gnd. electrical specifications recommended operating conditions unless otherwise noted. refer to ?functional block diagram? on page 2 and page 3 and typical application schematics on page 4 to page 6. 9v < v dd < 20 v, r td = 51.1k , r tc = 10k , c t = 470pf, t a = -40 c to +105 c , typical values are at t a = +25 c. boldface limits apply over the operating temperature range, -40c to +105c parameter test conditions min (note 7) typ max (note 7) units supply voltage start-up current, i dd v dd < start threshold - 95 140 a operating current, i dd r load , c outa,b = 0 - 5.0 8.0 ma c outa,b = 1nf - 7.0 12.0 ma uvlo start threshold 6.50 7.25 8.00 v uvlo stop threshold 6.00 6.75 7.50 v hysteresis 0.25 0.50 0.75 v reference voltage overall accuracy i vref = 0, -20ma 4.900 5.000 5.050 v long term stability t a = +125c, 1000 hours - 3 - mv fault voltage 4.10 4.55 4.75 v v ref good voltage 4.25 4.75 v ref - 0.05 v hysteresis 75 165 250 mv operational current (source) -20 --ma operational current (sink) 5 --ma current limit -25 - -100 ma current sense current limit threshold v error = v ref 0.55 0.6 0.65 v cs to out delay -35 50 ns cs sink current -10 - ma input bias current -1.00 - 1.00 a cs to pwm comparator input offset (ISL6741) (note 7) - 80 - mv
isl6740, ISL6741 8 fn9111.6 december 2, 2011 gain (ISL6741) a cs = v error / v cs -4 - v/v scset input impedance 1 --m sc setpoint accuracy -10 - % pulse width modulator v error input impedance 400 --k minimum duty cycle v error < cs offset (ISL6741) - - 0 % v error < c t valley voltage (isl6740) - - 0 % maximum duty cycle v error > 4.75v (note 9) - 83 - % v error to pwm comparator input offset (ISL6741) 0.4 1.0 1.25 v v error to pwm comparator input gain (ISL6741) - 0.25 - v error to pwm comparator input gain (isl6740) - 0.4 - v/v c t to pwm comparator input gain (isl6740) - 0.4 - v/v ss to pwm comparator input gain (isl6740) - 0.5 - v/v ss to pwm comparator input gain (ISL6741) - 0.2 - v/v oscillator frequency accuracy t a = +25c 333 351 369 khz frequency variation with v dd t = +105 c (f 20v - - f 9v )/f 9v -2 3 % t = -40 c (f 20v - - f 9v )/f 9v -2 3 % temperature stability -8 - % charge current gain 1.88 2.0 2.12 a/a discharge current gain 45 55 65 a/a c t valley voltage 0.75 0.80 0.85 v c t peak voltage 2.70 2.80 2.90 v rtd, rtc voltage r load = 0 - 2.000 - v synchronization input high threshold (vih), minimum 4.0 --v input low threshold (vil), maximum - - 0.8 v input impedance 4.5 - k input frequency range free running - 1.67 x free running hz high level output voltage (voh) i load = -1ma - 4.5 - v low level output voltage (vol) i load = 10a - - 100 mv sync output current voh > 2.0v -10 --ma sync output pulse duration (minimum) (note 8) 250 - 532 ns sync advance sync rising edge to gate falling edge, c gate = c sync = 100pf - 5 - ns soft-start charging current ss = 2v -45 -55 -75 a electrical specifications recommended operating conditions unless otherwise noted. refer to ?functional block diagram? on page 2 and page 3 and typical application schematics on page 4 to page 6. 9v < v dd < 20 v, r td = 51.1k , r tc = 10k , c t = 470pf, t a = -40 c to +105 c , typical values are at t a = +25 c. boldface limits apply over the operating temperature range, -40c to +105c (continued) parameter test conditions min (note 7) typ max (note 7) units
isl6740, ISL6741 9 fn9111.6 december 2, 2011 ss clamp voltage 4.35 4.5 4.65 v sustained overcurrent threshold voltage (isl6740) charged threshold minus: 0.20 0.25 0.30 v overcurrent/short circuit discharge current ss = 2v 13 18 23 a fault ss discharge current ss = 2v - 10.0 - ma reset threshold voltage 0.25 0.27 0.33 v fault fault high level output voltage (voh) i load = -10ma 2.85 3.5 - v fault low level output voltage (vol) i load = 10ma - 0.4 0.9 v fault rise time c load = 100pf - 15 - ns fault fall time c load = 100pf - 15 - ns output high level output voltage (voh) v ref - outa or outb, i out = -50ma -0.5 1.0 v low level output voltage (vol) outa or outb - gnd, i out = 50ma - 0.5 1.0 v rise time c gate = 1nf, v dd = 15v - 50 100 ns fall time c gate = 1nf, v dd = 15v - 40 80 ns thermal protection thermal shutdown 135 145 155 c thermal shutdown clear 120 130 140 c hysteresis, internal protection -15 - c reference, external protection 2.375 2.50 2.625 v hysteresis, external protection 18 25 30 a supply uvlo/inhibit input voltage low/inhibit threshold 0.97 1.00 1.03 v hysteresis, switched current amplitude 7 10 15 a input high clamp voltage 4.8 --v input impedance 1 --m notes: 7. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 8. sync pulse width is the greater of this value or the c t discharge time. 9. this is the maximum duty cycle achievable using the specified values of r tc , r td , and c t . larger or smaller maximum duty cycles may be obtained using other values for these comp onents. see equations 2 through 4. electrical specifications recommended operating conditions unless otherwise noted. refer to ?functional block diagram? on page 2 and page 3 and typical application schematics on page 4 to page 6. 9v < v dd < 20 v, r td = 51.1k , r tc = 10k , c t = 470pf, t a = -40 c to +105 c , typical values are at t a = +25 c. boldface limits apply over the operating temperature range, -40c to +105c (continued) parameter test conditions min (note 7) typ max (note 7) units
isl6740, ISL6741 10 fn9111.6 december 2, 2011 pin descriptions vdd - v dd is the power connection for the ic. to optimize noise immunity, bypass v dd to gnd with a ceramic capacitor as close to the v dd and gnd pins as possible. the total supply current, i dd , will be dependent on the load applied to outputs outa and outb. total i dd current is the sum of the quiescent current and the average output current. knowing the operating frequency, f sw , and the output loading capacitance charge, q, per output, the average output current can be calculated from: sync - a bidirectional synchronization signal used to coordinate the switching frequency of multip le units. synchronization may be achieved by connecting the sync signal of each unit together or by using an external master clock signal. the oscillator timing capacitor, c t , is always required regardless of the synchronization method used. th e paralleled unit with the highest oscillator frequenc y assumes control. self- synchronization is not recommended for oscillator frequencies above 900khz. for higher switching frequencies, an external clock with a pulse width less than one-half of the oscillator period must be used. rtc - this is the oscillator timing capacitor charge current control pin. a resistor is connected between this pin and gnd. the current flowing through the resistor determines the magnitude of the charge current. the charge current is nominally twice this current. the pwm maximum on time is determined by the timing capacitor charge duration. rtd - this is the oscillator timing capacitor discharge current control pin. a resistor is conne cted between this pin and gnd. the current flowing through the resistor determines the magnitude of the discharge current. the discharge current is nominally 50x this current. the pwm deadtime is determined by the timing capacitor discharge duration. ct - the oscillator timing capacitor is connected between this pin and gnd. verror - the inverting input of the pwm comparator. the error voltage is applied to this pin to control the duty cycle. increasing the signal level increases the duty cycle. the node may be driven with an external error am plifier or opto-coupler. typical performance curves figure 1. reference voltage vs temperature figure 2. oscillator c t discharge current gain figure 3. deadtime (td) vs capacitance figure 4. capacitance vs frequency 1.001 1.000 0.999 0.998 0.997 -40 -25 -10 5 20 35 50 65 80 95 110 temperature (c) normalized v ref 65 60 55 50 45 40 0 50 100 150 200 250 300 350 400 450 500 rtd current (a) c t discharge current gain 1?10 4 1?10 3 100 10 10 20 30 40 50 60 70 80 90 100 rtd (k ) deadtime - td (ns) 470 330 220 100 ct (pf) = 680 1000 1?10 6 1?10 4 60 70 80 90 100 rtc (k ) frequency (hz) 10 20 30 40 50 680 1000 330 470 220 100 ct (pf) = rtd = 10k 1?10 5 i out 2qf sw ? ? = a (eq. 1)
isl6740, ISL6741 11 fn9111.6 december 2, 2011 the isl6740, ISL6741 features a built-in soft-start. soft-start is implemented as a clamp on the error voltage input. ots - the non-inverting input to the over-temperature shutdown comparator. the signal input at this pin is co mpared to an internal threshold of v ref /2. if the voltage at this pin exceeds the threshold, the fault signal is asserted and the outputs are disabled until the condition clears. there is a nominal 25 a switched current source used for hysteresis. the amount of hysteresis is adjustable by vary ing the source impedance of the signal into this pin. ots may be used to monitor parameters other than temperature, such as voltage. any signal for which a high out-of-bounds monitor is desired may utilize the ots comparator. fault - the fault signal is asserted high whenever the outputs, outa and outb, are disabled. this occurs during an over- temperature fault, an input uv fault, a v ref uv fault, or during an overcurrent (isl6740) or short ci rcuit shutdown fault. fault can be used to disable synchronous rectifiers whenever the outputs are disabled. fault is a three-state output and is high impedance during the soft-start cycle. adding a pull-up resistor to vref or a pull-down resistor to ground determines the state of fault during soft-start. this feature allows the designer to use the fault signal to enable or disable output synchronous rectifiers during soft-start. uv - undervoltage monitor input pin. a resistor divider between the input source voltage and gnd sets the undervoltage lock out threshold. the signal is compared to an internal 1.00v reference to detect an undervoltage or inhibit condition. cs - this is the input to the current sense comparator(s). the ic has the pwm comparator for peak current mode control (ISL6741) and an overcurrent protection comparator. the overcurrent comparator threshold is set at 0.600v nominal. the cs pin is shorted to gnd at the end of each switching cycle. depending on the current sensin g source impedance, a series input resistor may be required due to the delay between the internal clock and the external power switch. this delay may allow an overlap such that the cs signal may be discharged while the current signal is still active. if the current sense source is low impedance, it will cause increased power dissipation. isl6740 - exceeding the overcurrent threshold will start a delayed shutdown sequence. once an overcurrent condition is detected, the soft-start charge current source is disabled. the soft-start capacitor begins discharging through a 25 a current source, and if it discharges to less than 4.25v (sustained overcurrent threshold), a shutdown condition occurs and the outa and outb outputs are forced low. when the soft-start voltage reaches 0.27v (reset threshold) a soft-start cycle begins. an overcurrent condition must be absent for 50 s before the delayed shutdown control resets. if the overcurrent condition ceases, and an additional 50 s period elapses before the shutdown threshold is reached, no shutdown occurs. the ss charging current is re-enabled and the soft-start voltage is allowed to recover. ISL6741 - the ISL6741 current mode controller does not shutdown due to an overcurrent condition. the pulse-by-pulse current limit characteristic of peak current mode control limits the output current to acceptable levels. gnd - reference and power ground for all functions on this device. due to high peak currents and high frequency operation, a low impedance layout is necessary. ground planes and short traces are highly recommended. outa and outb - alternate half cycle output stages. each output is capable of 0.5a peak currents for driving logic level power mosfets or mosfet drivers. each output provides very low impedance to overshoot and undershoot. vref - the 5.00v reference voltage output. +1%/-2% tolerance over line, load and operating temperature. bypass to gnd with a 0.047 f to 2.2 f ceramic capacitor. capacitors outside of this range may cause oscillation. ss - connect the soft-start timing capacitor between this pin and gnd to control the duration of soft-start. the value of the capacitor determines the rate of in crease of the duty cycle during start up, controls the overcurrent shutdown delay (isl6740), and the overcurrent and short circ uit hiccup re start period. scset - sets the duty cycle threshold that corresponds to a short circuit condition. a resistive divider between r tc and gnd or r td and gnd, or a voltage between 0v and 2v may be used to adjust the scset threshold. if using a resi stor divider from either rtc or rtd, the impedance to gnd affe cts the oscillator timing and should be considered when de termining the oscillator timing components. connecting scset to gnd disables short circuit shutdown and hiccup. functional description features the isl6740, ISL6741 pwms are an excellent choice for low cost bridge and push-pull topologies for applications requiring accurate duty cycle and deadtime control. with its many protection and control features, a highly flexible design with minimal external components is possible. among its many features are current mode contro l (ISL6741), adjustable soft- start, overcurrent protection, th ermal protection, bidirectional synchronization, fault indication, and adjustable frequency. oscillator the isl6740, ISL6741 have an os cillator with a programmable frequency range to 2mhz, which can be programmed with two resistors and capacitor. the use of three timing elements, r tc , r td , and c t allow great flexibility and precision when setting the oscillator frequency. the switching period may be considered the sum of the timing capacitor charge and discharge durations. the charge duration is determined by r tc and c t . the discharge duration is determined by r td and c t . t c 0.5 r tc ? c t ? s (eq. 2) t d 0.02 r td ? c t ? s (eq. 3) t sw t c t d + 1 f sw ---------- - == s (eq. 4)
isl6740, ISL6741 12 fn9111.6 december 2, 2011 where t c and t d are the charge and discha rge times, respectively, t sw is the oscillator free running period, and f is the oscillator frequency. one output switching cycle requires two oscillator cycles. the actual times will be slightly longer than calculated due to internal propagation delays of approximately 10ns/transition. this delay ads di rectly to the switching duration, but also causes overshoot of the timing capacitor peak and valley voltage thresholds, effectively increasing the peak-to-peak voltage on the timing capacitor. additionally, if very low charge and discharge currents are used, there will be increased error due to the input impedance at the c t pin. the maximum duty cycle, d, and percent deadtime, dt, can be calculated from: implementing synchronization the oscillator can be synchronized to an external clock applied to the sync pin or by connecting the sync pins of multiple ics together. if an external master clock signal is used, the free running frequency of the oscillator should be ~10% slower than the desired synchronous frequenc y. the external master clock signal should have a pulse width greater than 20ns. the sync circuitry will not respond to an external signal during the first 60% of the oscillator switching cycl e. self-synchronization is not recommended for oscillator fr equencies above 900 khz. for higher switching frequencies, an external clock with a pulse width less than one-half of the oscillator period must be used. the sync input is edge triggered and its duration does not affect oscillator operation. however, the deadtime is affected by the sync frequency. a higher frequency signal applied to the sync input will shorten the deadtime. the shortened deadtime is the result of the timing capacitor charge cycle being prematurely terminated by the external sync pulse. consequently, the timing capacitor is not fully charged when the discharge cycle begins. this effect is only a concern when an external master clock is used, or if units with different operating frequencies are paralleled. soft-start operation the isl6740, ISL6741 feature a soft-start using an external capacitor in conjunction with an in ternal current source. soft-start reduces stresses and surge currents during start up. upon start up, the soft-start circuitry clamps the error voltage input (v error pin) indirectly to a value equal to the soft-start voltage. the soft-start clamp does not actually clamp the error voltage input as is done in many implementations. rather the pwm comparator has two inverting inputs such that the lower voltage is in control. the output pulse width increase s as the soft-start capacitor voltage increases. this has the effect of increasing the duty cycle from zero to the regulation pu lse width during the soft-start period. when the soft-start voltage exceeds the error voltage, soft-start is completed. soft-start occurs during start-up, after recovery from a fault conditio n or overcurrent/short circuit shutdown. the soft-start voltage is clamped to 4.5v. the fault signal output is high impedance during the soft-start cycle. a pull-up resistor to vref or a pull-down resistor to ground should be added to achieve the de sired state of fault during soft- start. gate drive the isl6740, ISL6741 are capable of sourcing and sinking 0.5a peak current, but are primarily intended to be used in conjunction with a mosfet driver due to the 5v drive level. to limit the peak current through the ic, an external resistor may be placed between the totem-pole output of the ic (outa or outb pin) and the gate of the mosfet. this small series resistor also damps any oscillations caused by the resonant tank of the parasitic inductances in the traces of the board and the fet?s input capacitance. undervoltage monitor and inhibit the uv input is used for input source undervoltage lockout and inhibit functions. if the node voltage falls below 1.00v a uv shutdown fault occurs. this may be caused by low source voltage or by intentional grounding of the pin to disable the outputs. there is a nominal 10 a switched current source used to create hysteresis. the current source is active only during an uv/inhibit fault; otherwise, it is inactive and does not affect the node voltage. the magnitude of the hysteresis is a function of the external resistor divider impeda nce. if the resistor divider impedance results in too little hysteresis, a series resistor between the uv pin and the divider may be used to increase the hysteresis. a soft-start cycle be gins when the uv/inhibit fault clears. the voltage hysteresis created by the switched current source and the external impedance is ge nerally small due to the large resistor divider ratio required to scale the input voltage down to the uv threshold level. a small capacitor placed between the uv input and ground may be required to filter noise out. as v in decreases to a uv condition, the threshold level is: d t c t sw --------- - = (eq. 5) dt 1 d ? = (eq. 6) figure 5. uv hysteresis v in r1 r2 r3 1.00v 10 a on + - v in down () r1 r2 + r2 --------------------- - = v (eq. 7)
isl6740, ISL6741 13 fn9111.6 december 2, 2011 the hysteresis voltage, v, is: setting r3 equal to zero result s in the minimum hysteresis, and yields: as v in increases from a uv condition, the threshold level is: overcurrent operation isl6740 - overcurrent delayed shutdown is enabled once the soft-start cycle is complete. if an overcurrent condition is detected, the soft-start charging current source is disabled and the soft-start capacitor is allowed to discharge through a 15 a source. at the same time a 50 s re-triggerable one-shot timer is activated. it remains active for 50 s after the overcurrent condition ceases. if the soft-start capacitor discharges by more then 0.25v to 4.25v, the output is disabled and the fault signal asserted. this state continues unti l the soft-start voltage reaches 270mv, at which time a new soft-s tart cycle is initiated. if the overcurrent condition stops at least 50 s prior to the soft-start voltage reaching 4.25v, the soft-start charging currents revert to normal operation and the soft-start voltage is allowed to recover. the duration of the oc shutdown period can be increased by adding a resistor between vref an d ss. the value of the resistor must be large enough so that the minimum specified ss discharge current is not exceeded. using a 422k resistor, for example, will result in a small current being injected into ss, effectively reducing the discharge current. this will increase the off time by about 60%, nominally. the external pull-up resistor will also decrease the ss dura tion, so its effect should be considered when selecting the value of the ss capacitor. latching oc shutdown is also possible by using a lower valued resistor between vref and ss. if the ss node is not allowed to discharge below the ss reset threshold, the ic will not recover from an overcurrent fault. the va lue of the resistor must be low enough so that the maximum specified discharge current is not sufficient to pull ss below 0.33v. a 200k resistor, for example, prevents ss from discharging below ~0.4v. again, the external pull-up resistor will decrease the ss duration, so its effect should be considered when selecting the value of the ss capacitor. ISL6741 - overcurrent results in pulse-by-pulse duty cycle reduction as occurs in any peak current mode controller. this results in a well controlled decrease in output voltage with increasing current beyond th e overcurrent threshold. an overcurrent condition in the is l6741 will not cause a shutdown. short circuit operation a short circuit condition is defined as the simultaneous occurrence of current limit and a reduced duty cycle. the degree of reduced duty cycle is user adjustable using the scset input. a resistor divider between either r td or r tc and gnd to rcset sets a threshold that is compared to the voltage on the timing capacitor, c t . the resistor divi der percentage corresponds to the fraction of the maximum duty cycle below which a short circuit may exist. if the timing capacitor voltage fails to exceed the threshold before an overcurrent pulse is detected, a short circuit condition exists. a shutdown and so ft-start cycle will begin if 8 short circuit events occur within 32 oscillator cycles. connecting scset to gnd disables this feature. since the current sourced from both r tc and r td determine the charge and discharge currents for the timing capacitor, the effect of the scset divider must be included in the timing calculations. typically the resistor between r tc and gnd is formed by two series resistors with the cent er node connected to scset. alternatively, scset may be set using a voltage between 0v and 2v. this voltage divided by 2 determines the percentage of the maximum duty cycle that corresponds to a short circuit when current limit is active. for example, if the maximum duty cycle is 95% and 1v is applied to scset, then the short circuit duty cycle is 50% of 95% or 47.5%. fault conditions a fault condition occurs if v ref falls below 4.65v, the uv input falls below 1.00v, the thermal protection is triggered, or if ots faults. when a fault is detected, outa and outb outputs are disabled, the fault signal is asse rted, and the soft-start capacitor is quickly discharged. when the fault condition clears and the soft-start voltage is below the re set threshold, a soft-start cycle begins. the fault signal is high impedance during the soft-start cycle. an overcurrent condition that resu lts in shutdown (isl6740), or a short circuit shutdown also cause assertion of the fault signal. the difference between a current fault and the faults described earlier is that the soft-start capacitor is not quickly discharged. the initiation of a new soft-start cycle is delayed while the soft- start capacitor is discharged at a 15 a rate. this keeps the average output current to a minimum. thermal protection two methods of over-temperature protection are provided. the first method is an on board temperature sensor that protects the device should the junction temperature exceed 145 c. there is approximately 15 c of hysteresis. the second method uses an internal comparator with a 2.5v reference (v ref /2). the non-inverting input to the comparator is accessible through the ots pin. a thermistor or thermal sensor located at or near the area of interest may be connected to this input. there is a nominal 25 a switched current source used to create hysteresis. the current source is active only during an ot fault; otherwise, it is inactive and does not affect the node voltage. the magnitude of the hysteresis is a function of the external resistor divider impedance. either a positive temperature coefficient (ptc) or a negative temperature v10 5 ? r1 r3 r1 r2 + r2 --------------------- - ?? ?? ? + ?? ? = v (eq. 8) v10 5 ? r1 ? = v (eq. 9) v in up () v in down () v + = v (eq. 10)
isl6740, ISL6741 14 fn9111.6 december 2, 2011 coefficient (ntc) thermistor may be used. if a ntc is desired, position r1 may be substituted. if a ptc is desired, then position r2 may be substituted. the threshold with increasing temperature is set by making the fixed resistance equal in value to the thermistor resistance at the desired trip temperature. v th = 2.5v and r1 = r2 (hot) to determine the value of the hysteresis resistor, r3, select the value of thermistor resistance that corresponds to the desired reset temperature. if the hysteresis resistor, r3, is not desired, the value of the thermistor resistance at th e reset temperature can be determined from: the ots comparator may also be used to monitor signals other than suggested above. it may also be used to monitor any voltage signal for which an excess requires a response as described above. input or output voltage monitoring are examples of this. ground plane requirements careful layout is essential for satisfactory operation of the device. a good ground plane must be employed. v dd should be bypassed directly to gnd with good high frequency capacitance. typical application the typical application schematic features the isl6740 in an unregulated half-bridge dc/dc converter configuration, often referred to as a dc transformer or bus regulator. the isl6740eval1 demonstration unit implements this design and is available for evaluation. the input voltage range is 48 10%vdc. the output is a nominal 12v when the input voltage is at 48v. since this is an unregulated topology, the output voltage will vary proportionately with input voltage. the load regula tion is a function of resistance between the source and the converter output. the output is rated at 8a. circuit element descriptions the converter design may be broken down into the following functional blocks: input filtering: l 1 , c 1 , r 1 half-bridge capacitors: c 2 , c 3 isolation transformer: t 1 primary snubber: c 13 , r 10 start bias regulator: c r3 , r 2 , r 7 , c 6 , q 5 , d 1 supply bypass components: r 3 , c 15 , c 4 , c 5 main mosfet power switch: qh, ql current sense network: t 2 , c r1 , c r2 , r 5 , r 6 , r 11 , c 10 , c 14 control circuit: u 3 , r t1 , r 14 , r 19 , r 13 , r 15 , r 17 , r 18 , c 16 , c 18 , c 17 output rectification and filtering: q r1 , q r2 , q r3 , q r4 , l 2 , c 9 , c 8 secondary snubber: r 8 , r 9 , c 11 , c 12 fet driver: u 1 zvs resonant delay (optional): l 3 , c 7 design criteria the following design requirements were selected: switching frequency, fsw: 235khz v in : 48 10%v v out : 12v (nominal) @ i out = 8a p out : 100w efficiency: 95% ripple: 1% transformer design the design of a transformer for a half-bridge application is a straight forward affair, although it erative. it is a process of many compromises, and even experienced designers will produce different designs when presented with identical requirements. the iterative design process is not presented here for clarity. figure 6. ots hysteresis v ref r1 r2 r3 v ref /2 25 a on + - v ref r3 10 5 r1 r2 ? () ? r1 r2 ? ? r1 r2 + --------------------------------------------------------------------- - = (eq. 11) r1 2.5 r2 ? 2.5 10 5 ? r2 ? ? ---------------------------------------- - = ntc () (eq. 12) r2 2.5 r1 ? 2.5 10 5 ? r1 ? + ----------------------------------------- = ptc () (eq. 13)
isl6740, ISL6741 15 fn9111.6 december 2, 2011 the abbreviated design process follows: ? select a core geometry suitable for the application. constraints of height, footprin t, mounting preference, and operating environment will affect the choice. ? determine the turns ratio. ? select suitable core material(s). ? select maximum flux density desired for operation. ? select core size. core size will be dictated by the capability of the core structure to store the required energy, the number of turns that have to be wound, and the wire gauge needed. often the window area (the space used for the windings) and power loss determine the final core size. ? determine maximum desired flux density. depending on the frequency of operation, the co re material selected, and the operating environment, the allowed flux density must be determined. the decision of what flux density to allow is often difficult to determine initially. usually the highest flux density that produces an acceptable design is used, but often the winding geometry dictates a larger core than is indicated based on flux density alone. ? determine the number of primary turns. ? select the wire gauge for each winding. ? determine winding order and insulation requirements. ?verify the design. for this application we have se lected a planar structure to achieve a low profile design. a pq style core was selected because of its round center leg cross section, but there are many suitable core styles available. since the converter is operating open loop at nearly 100% duty cycle, the turns ratio, n, is simply the ratio of the input voltage to the output voltage divided by 2. the factor of 2 divisor is due to the half-bridge topology. only half of the input voltage is applied to the primary of the transformer. a pc44hpq20/6 ?e-core? plus a pc44pq20/3 ?i-core? from tdk were selected for the transformer core. the ferrite material is pc44. the core parameter of concern fo r flux density is the effective core cross sectional area, ae. for the pq core pieces selected: ae = 0.62cm 2 or 6.2e -5m 2 using faraday?s law, v = n d /dt, the number of primary turns can be determined once the maximum flux density is set. an acceptable bmax is ultimately determined by the allowable power dissipation in the ferrite material and is influenced by the lossiness of the core , core geometry, operating ambient temperature, and air flow. the tdk datasheet for pc44 material indicates a core loss factor of ~400mw/cm 3 with a 2000 gauss 100khz sinusoidal excita tion. the application uses a 235khz square wave excitation, so no direct comparison between the application and the data can be made. interpolation of the data is required. the core volume is approximately 1.6cm 3 , so the estimated core loss is 1.28w of dissipation is significant for a core of this size. reducing the flux density to 1200 gauss will reduce the dissipation by about the same pe rcentage, or 40%. ultimately, evaluation of the transformer?s performance in the application will determine what is acceptable. from faraday?s law and using 1200 gauss peak flux density ( b = 2400 gauss or 0.24 tesla) rounding up yields 4 turns for the primary winding. the peak flux density using 4 turns is ~1100 gauss. from equation 1, the number of secondary turns is 2. the volts/turn for this design ranges from 5.4v at v in = 43v to 6.6v at v in = 53v. therefore, the synchronous rectifier (sr) windings may be set at 1 turn each with proper fet selection. selecting 2 turns for the synchronous rectifier windings would also be acceptable, but the ga te drive losses would increase. the next step is to determine the equivalent wire gauge for the planar structure. since each seco ndary winding conducts for only 50% of the period, the rms current is where d is the duty cycle. since an fr-4 pwb planar winding structure was selected, the width of the copper traces is limited by the window area width, and the number of layers is limited by the window area height. the pq core selected has a usable window area width of 0.165 inches. allowing one turn per layer and 0.020 inches clearance at the edges allows a maximum trace width of 0.125 inches. using 100 circular mils(c.m.)/a as a guideline for current density, and from equation 17, 707c.m. are required for each of the secondary windings (a circular mil is the area of a circle 0.001 inches in diameter). converting c.m. to figure 7. transformer schematic n p n sr n s n s n sr n v in v out 2 ? ---------------------- 48 12 2 ? --------------- - 2 === (eq. 14) p loss mw cm 3 ----------- cm 3 f act f meas --------------- ? ? 0.4 1.6 200khz 100khz -------------------- - ? ? 1.28 == w (eq. 15) n v in t on ? 2a e b ? ? ---------------------------- - 53210 6 ? ? ? 26.210 5 ? 0.24 ? ? ? ----------------------------------------------------- - 3.56 == = turns (eq. 16) i rms i out d ? 10 0.5 ? 7.07 === a (eq. 17)
isl6740, ISL6741 16 fn9111.6 december 2, 2011 square mils yields 555mils 2 (0.785 sq. mils/c.m.). dividing by the trace width results in a copper thickness of 4.44 mils (0.112mm). using 1.3 mils/oz. of copper requires a copper weight of 3.4oz. for reasons of cost, 3oz. copper was selected. one layer of each secondary winding also contains the synchronous rectifier winding. for this layer the secondary trace width is reduced by 0.025 inches to 0.100 inches(0.015 inches for the sr winding trace width and 0.010 inches spacing between the sr winding and the secondary winding). the choice of copper weight may be validated by calculating the dc copper losses of the secondary winding as follows. ignoring the terminal and lead-in resistance , the resistance of each layer of the secondary may be approximated using equation 18. where r = winding resistance = resistivity of copper = 669e-9 -inches at 20c t = thickness of the copper (3 oz.) = 3.9e-3 inches r 2 = outside radius of the coppe r trace = 0.324 or 0.299 inches r 1 = inside radius of the copper trace = 0.199 inches the winding without the sr winding on the same layer has a dc resistance 2.21m . the winding that shares the layer with the sr winding has a dc resistance of 2.65m . with the secondary configured as a 4 turn center tapped winding (2 turns each side of the tap), the total dc power lo ss for the secondary at +20c is 486mw. the primary windings have an rm s current of approximately 5a (i out x n s /n p at ~ 100% duty cycle). the primary is configured as 2 layers, 2 turns per layer to minimize the winding stack height. allowing 0.020 inches edge clearance and 0.010 inches between turns yields a trace width of 0.0575 inches. ignoring the terminal and lead-in resistance, and usin g equation 18, the inner trace has a resistance of 4.25m , and the outer trace has a resistance of 5.52m . the resistance of the primary then is 19.5m at +20c. the total dc power loss for the secondary at +20c is 489mw. improved efficiency and thermal performance could be achieved by selecting heavier copper weight for the windings. evaluation in the application will determine its need. the order and geometry of the windings affects the ac resistance, winding capacitance, and leakage inductance of the finished transformer. to mitigate these effects, interleaving the windings is necessary. the pr imary winding is sandwiched between the two secondary wi ndings. the winding layout appears below. r 2 t r 2 r 1 ---- - ?? ?? ?? ln ? ----------------------- - = (eq. 18) figure 7a. top layer: 1 turn secondary and sr windings figure 7b. int. layer 1: 1 turn secondary winding figure 7c. int. layer 2: 2 turns primary winding figure 7d. int. layer 3: 2 turns primary winding
isl6740, ISL6741 17 fn9111.6 december 2, 2011 mosfet selection the criteria for selection of the primary side half-bridge fets and the secondary side synchronous rect ifier fets is largely based on the current and voltage rating of the device. however, the fet drain-source capacitance and ga te charge cannot be ignored. the zero voltage switch (zvs) tran sition timing is dependent on the transformer?s leakage inductan ce and the capacitance at the node between the upper fet source and the lower fet drain. the node capacitance is comprised of the drain-source capacitance of the fets and the transformer parasitic capacitance. the leakage inductance and capacitance form an lc resonant tank circuit which determines the duration of the transition. the amount of energy stored in the lc tank circuit determines the transition voltage amplitude. if the leakage inductance energy is too low, zvs operation is not possible and near or partial zvs operation occurs. as the leakage energy increases, the voltage amplitude increases until it is cl amped by the fet body diode to ground or v in , depending on which fet conducts. when the leakage energy exceeds the minimum required for zvs operation, the voltage is clamped until the energy is transferred. this behavior increases the time window for zvs operation. this behavior is not without conseque nces, however. the transition time and the period of time during which the voltage is clamped reduces the effective duty cycle. the gate charge affects the swit ching speed of the fets. higher gate charge translates into hi gher drive requirements and/or slower switching speeds. the energy required to drive the gates is dissipated as heat. the maximum input voltage, v in , plus transient voltage, determines the voltage rating required. with a maximum input voltage of 53v for this applicatio n, and if we allow a 10% adder for transients, a voltage rating of 60v or higher will suffice. the rms current through the each primary side fet can be determined from equation 17, subs tituting 5a of primary current for i out . the result is 3.5a rms. fairchild fds3672 fets, rated at 100v and 7.5a (r ds(on) = 22m ), were selected for the half- bridge switches. the synchronous rectifier fets must withstand approximately one half of the input voltage a ssuming no switching transients are present. this suggests a devi ce capable of withstanding at least 30v is required. empirical testing in the circuit revealed switching transients of 20v were present across the device indicating a rating of at least 60v is required. the rms current rating of 7.07a for each sr fet requires a low r ds(on) to minimize conduction losses, which is difficult to find in a 60v device. it was decided to use two devices in parallel to simplify the thermal design. two fairchild fds5670 devices are used in parallel for a total of four sr fe ts. the fds5670 is rated at 60v and 10a (r ds(on) = 14m ). oscillator component selection the desired operating frequency of 235khz for the converter was established in ?design criteria? on page 14. the oscillator frequency operates at twice the frequency of the converter because two clock cycles are required for a complete converter period. during each oscillator cycle the timing capacitor, c t , must be charged and discharged. determining the required discharge time to achieve zero voltage switching (zvs) is the critical design goal in selecting the timing comp onents. the discharge time sets the deadtime between the two outputs, and is the same as zvs transition time. once the discharge time is determined, the remainder of the period becomes the charge time. the zvs transition duration is determined by the transformer?s primary leakage inductance, l lk , by the fet coss, by the transformer?s parasitic winding capacitance, and by any other parasitic elements on the node. the parameters may be figure 7e. int. layer 4: 1 turn secondary winding figure 7f. bottom layer: 1 turn secondary and sr windings figure 7g. pwb dimensions ? 0.689 0.807 0.639 0.403 0.169 0.000 1.054 0.774 0.479 0.184 0.000 ? 0.358
isl6740, ISL6741 18 fn9111.6 december 2, 2011 determined by measurement, calculation, estimate, or by some combination of these methods. device output capacitance, coss, is non-linear with applied voltage. to find the equivalent discrete capacitance, cfet, a charge model is used. using a known current source, the time required to charge the mosfet drain to the desired operating voltage is determined and the equivalent capacitance is calculated. once the estimated transition ti me is determined, it must be verified directly in the applic ation. the transformer leakage inductance was measured at 125nh and the combined capacitance was estimated at 2000pf. calculations indicate a transition period of ~ 25ns. verification of the performance yielded a value of t d closer to 45ns. the remainder of the switching ha lf-period is the charge time, t c , and can be found from where f s is the converter switching frequency. using figure 4, the capacitor value appropriate to the desired oscillator operating frequency of 470khz can be selected. a c t value of 100pf, 220pf, or 330pf is appropriate for this frequency. a value of 220pf was selected. to obtain the proper value for r td , equation 3 is used. since there is a 10ns propagation delay in the oscillator circuit, it must be included in the calculation. the value of r td selected is 8.06k . a similar procedure is used to determine the value of r tc using equation 2. the value of r tc selected is the series combination of 17.4k and 1.27k . see section ?overcurrent component selection? on page 18 for further explanation. output filter design the output filter inductor and capacitor selection is simple and straightforward. under steady state operating conditions the voltage across the inductor is very small due to the large duty cycle. voltage is applied across the inductor only during the switch transition time, about 45ns in this application. ignoring the voltage drop across the sr fets, the voltage across the inductor during the on time with v in = 48v is: where v l is the inductor voltage v s is the voltage across the secondary winding v out is the output voltage if we allow a current ramp, i, of 5% of the rated output current, the minimum inductance required is: an inductor value of 1.4 h, rated for 18a was selected. with a maximum input voltage of 53v, the maximum output voltage is about 13v. the closest higher voltage rated capacitor is 16v. under steady state operat ing conditions the ripple current in the capacitor is small, so it would seem appropriate to have a low ripple current rated capacitor. however, a high rated ripple current capacitor was selected based on the nature of the intended load, multiple buck regulators. to minimize the output impedance of the filter, a sanyo oscon 16sh150m capacitor in parallel with a 22 f ceramic capacitor were selected. overcurrent component selection there are two circuit areas to consider when selecting the components for overcurrent protection, current limit and short circuit shutdown. the current limit threshold is fixed at 0.6v while the short circuit threshold is set to a fraction of the duty cycle the designer wishes to define as a short circuit. the current level that corresponds to the overcurrent threshold must be chosen to allow for the dynamic behavior of an open loop converter. in particular, the low inductor ripple current under steady state operation increases significantly as the duty cycle decreases. t zvs l lk 2c oss c xfrmr + () ? 2 ----------------------------------------------------------------- - s (eq. 19) cfet ichg t ? v ------------------- = f (eq. 20) t c 1 2f s ? --------------- t d ? 1 223510 3 ? ? ----------------------------------- 45 10 9 ? ? ? 2.08 == = s (eq. 21) v l v s v out ? v in n s 1d ? () ? ? 2n p --------------------------------------------- 250 == mv (eq. 22) l v l t on ? i --------------------- - 0.25 2.08 ? 0.5 ----------------------------- 1.04 == h (eq. 23) figure 8. steady state secondary winding voltage and inductor current 14 13 12 11 10 9 8 0.9950 0.9960 0.9970 0.9980 0.9990 1.000 time (ms) v (l1:1) i (l1)
isl6740, ISL6741 19 fn9111.6 december 2, 2011 figures 8 and 9 show the behavior of the inductor ripple under steady state and overcurrent cond itions. in this example, the peak current limit is set at 11a. the peak current limit causes the duty cycle to decrease resulting in a reduction of the average current through the inductor. the im plication is that the converter can not supply the same output current in current limit that it can supply under steady state conditions. the peak current limit setpoint must take this behavior into consideration. a 3.32 current sense resistor was selected for the rectified secondary of current transformer t2, corresponding to a peak current limit setpoint of 16.5a. the short circuit protection involves setting a voltage between 0 and 2v on the scset pin. the applied voltage divided by 2 is the percent of maximum duty cycle that corresponds to a short circuit when the peak current limit is active. a divider from rtc to ground provides an easy method to achieve this. the divider between rtc and gnd formed by r13 and r15 determines the percent of maximum duty cycle that corresponds to a short circuit. the divider ratio formed by r13 and r15 is: therefore, the duty cycle that corresponds to a short circuit is 6.8% of d max (97.9%), or ~6.6%. performance the major performance criteria for the converter are efficiency, and to a lesser extent, load regula tion. efficiency, load regulation and line regulation performance are demonstrated in the following figures. as expected, the output voltage varies considerably with line and load when compared to an equivalent converter with closed loop feedback. however, for applications where tight regulation is not required, such as those application that use downstream dc/dc converters, this design approach is viable. figure 9. secondary winding voltage and inductor current during current limit operation 0.986 0.988 0.990 0.992 0.994 1.000 time (ms) 0.996 0.998 15 10 5 v (l1:1) i (l1) r15 r13 r15 + ---------------------------- - 1.27k 1.27k 17.4k + ------------------------------------- 0.068 == (eq. 24) figure 10. efficiency vs load v in = 48v t load current (a) efficiency (%) 100 95 90 85 80 75 70 0 1234567 8 9 figure 11. load regulation at v in = 48v load current (a) output voltage (v) 12.5 12.25 12.00 11.75 11.50 11.25 11 01234567 8 9 figure 12. line regulation at i out = 1a input voltage (v) 45 46 47 48 49 50 51 52 53 54 14.0 13.5 13.0 12.5 12.0 11.5 11.0 ouput voltage (v)
isl6740, ISL6741 20 fn9111.6 december 2, 2011 waveforms typical waveforms can be found in the following figures. figure 13 shows the output voltage during start up. figure 14 shows the output voltag e ripple and noise at a 5a load. figures 15 and 16 show the voltage waveforms at the switching node shared by the upper fet source and the lower fet drain. in particular, figure 16 shows near zv s operation at 8a of load when the upper fet is turning off and the lower fet turning on. there is insufficient energy stored in the leakage inductance to allow complete zvs operation. however, since the energy stored in the node capacitance is proportional to v 2 , a significant portion of the energy is still recovered. figure 17 shows the switching transition between outputs, outa and outb during steady state operation. the deadtime duration of 48.6ns is clearly shown. figure 13. output soft-start figure 14. output ripple and noise (20mhz bw) figure 15. fet drain-source voltage figure 16. fet d-s voltage near-zvs transition figure 17. outa to outb transition
isl6740, ISL6741 21 fn9111.6 december 2, 2011 adding line only regu lation - feed forward output voltage variation caused by changes in the supply voltage may be virtually removed through a technique known as feed forward compensation. using feed forward, the duty cycle is directly controlled based on changes in the input voltage only. no closed loop feedback system is required. voltage feed forward may be implemented as shown in figure 18. the circuit provides feed forward compensation for a 2:1 input voltage range. resistors r 100 and r 101 set the input voltage divider to generate a 1v sign al at the input voltage that corresponds to maximum duty cycle (v in minimum). resistors r 109 , r 110 , and r 111 form a voltage divider from vref to create reference voltages for the amplifiers. the first stage uses u 100a , r 102 , r 103 , r 104 , and c 100 to form a unity gain inverting amplifier. its output varies inversely with input voltage and ranges from 1v to 2v. the bandwidth of the circuit may be controlled by varying the value of c 100 . the gain of the first amplifier stage is: where: v a = output voltage of u 100a v d = the input divider voltage the second stage uses u 100b , r 105 , r 106 , r 107 , and r 108 to form a summing amplifier which offsets the first stage output by 0.8v (the value of c t valley voltage). the signal applied to the v error input now matches the offset and amplitude of the oscillator sawtooth so that the du ty cycle varies linearly from 100% to 50% of maximum with a 2:1 input voltage variation. component list reference designator value description c 1 1.0 f capacitor, 1812, x7r, 100v, 20% tdk c4532x7r2a105m c 2 , c 3 3.3 f capacitor, 1812, x5r, 50v, 20% tdk c4532x5r1h335m c 4 , c 6 1.0 f capacitor, 0805, x5r, 16v, 10% tdk c2012x5r1c105k c 5 , c 15 , c 16 0.1 f capacitor, 0603, x7r, 50v, 10% tdk c1608x7r1h104k c 7 open capacitor, 0603, open c 8 22 f capacitor, 1812, x5r, 16v, 20% tdk c4532x5r1c226m c 9 150 f capacitor, radial, sanyo 16sh150m c 10 , c 11 , c 12 , c 13 , c 14 1000pf capacitor, 0603, x7r, 50v, 10% tdk c1608x7r1h102k c 17 220pf capacitor, 0603, cog, 16v, 5% tdk c1608cog1c221j c 18 0.047 f capacitor, 0603, x7r, 16v, 10% tdk c1608x7r1c473k c r1 , c r2 diode, schottky, bat54s c r3 diode, schottky, bat54 d 1 zener, 10v, philips bzx84-c10 l 1 190nh pulse, p2004t l 2 1.5 hpulse, pg0077.142 l 3 short jumper or optional discrete leakage inductance q 5 transistor, on mjd31c q l , q h fet, fairchild fds3672 q r1 , q r2 , q r3 , q r4 fet, fairchild fds5670 r 1 , r 10 3.3 resistor, 2512, 5% r 2 3.01k resistor, 2512, 1% r 3 , r 6 10.0 resistor, 0603, 1% r 5 3.32 resistor, 0603, 1% r 7 75.0k resistor, 0805, 1% r 8 , r 9 20.0 resistor, 0805, 1% r 11 100 resistor, 0603, 1% r 12 8.06k resistor, 0603, 1% r 13 17.4k resistor, 0603, 1% r 14 open resistor, 0603, open r 15 1.27k resistor, 0603, 1% r 17 97.6k resistor, 0603, 1% r 18 3.01k resistor, 0603, 1% r 19 , r t1 10.0k resistor, 0603, 1% t 1 midcom 31718 t 2 pulse p8205t u 1 intersil hip2101ib u 3 isl6740ib figure 18. voltage feed forward circuit + - + - 1.5v 0.8v r102 100k r101 2k r100 69.8k +vin vref r109 3.48k r110 698 r111 806 r104 100k r106 100k r105 100k r107 100k r108 100k r103 49.9k c100 1nf to verror u100a u100b v a v d 3.00 + ? = v (eq. 25)
isl6740, ISL6741 22 fn9111.6 december 2, 2011 other duty ranges are possible, but are still limited to a 2:1 ratio. the voltage applied to v error must be scaled to the peak-to- peak voltage on c t , and offset by the valley voltage. since the peak-to-peak c t voltage is 2.00v nominal, the voltage at the output of u100a must be divided by 2.0v to obtain the desired duty cycle. for example, if an 80% duty cycle was required at the minimum operating voltage, the output of u100a must be 1.60v (80% of 2.00v). from (equation 25), the divider voltage must be set to 1.4v for the input voltage that corresponds to the 80% duty cycle. it should be noted that the synchronous rectifiers (srs), being driven from the transformer secondary, are only gated on during the on time of the primary fets. conduction continues through the body diodes during the off time when operating in continuous inductor current mo de. this mode of operation usually results in significant co nduction and switching losses in the sr fets. these losses may be reduced considerably by either adding schottky diodes in parallel to the sr fets or by driving the sr fets directly with a control signal. adding regulation - closed loop feedback the second typical application schematic adds closed loop feedback with isolation. the isl6740eval2z demonstration platform implements this design and is available for evaluation. the input voltage range was increased to 36v to 75v, which necessitates a few modifications to the open loop design. the output inductor value was increased to 4.0 h, schottky rectifier cr4 was added to minimize sr fet body diode conduction, the turns ratio of the main transformer was changed to 4:3, and the synchronous rectifier gate driv es were modified. the design process is essentially the same as it was for the unregulated version, so only the feedback control loop design will be discussed. the major components of the feedback control loop are a programmable shunt regulator and an opto-coupler. the opto- coupler is used to transfer the error signal across the isolation barrier. the opto-coupler offers a convenient means to cross the isolation barrier, but it adds complexity to the feedback control loop. it adds a pole at about 10k hz and a significant amount of gain variation due the current tran sfer ratio (ctr). the ctr of the opto-coupler varies with initial tolerance, temperature, forward current, and age. a block diagram of the feedback control loop follows in figure 19. the loop compensation is placed around the error amplifier (ea) on the secondary side of the converter. a type 3 error amplifier configuration was selected. the control to output transfer fu nction may be represented as [1] where: r o = output load resistance l = output inductance c = output capacitance r c = output capacitance esr v s = sawtooth ramp amplitude gain and phase plots of (equation 26) appear below using l = 4.0 h, c = 150 f, rc = 28m , ro = 1.2 , and vin = 75v. figure 19. control loop block diagram pwm power stage z 1 z 2 ref + - isolation error amplifier v out figure 20. type 3 error amplifier ref + - v out v err v o v c ----- v in v s 2 ? --------------- n s n p ------ - ? 1 s z ------ + 1 s q () o --------------- - s o ------ - ?? ?? 2 ++ ------------------------------------------------ ? = (eq. 26) q r o o l ? --------------- = o 1 lc ---------- - = or f o 1 2 lc ------------------ = z 1 r c c --------- - = or f z 1 2 r c c ----------------- - =
isl6740, ISL6741 23 fn9111.6 december 2, 2011 the type 3 compensation config uration has three poles and two zeros. the first pole is at the or igin, and provides the integration characteristic which results in excellent dc regulation. referring to the typical application schema tic for the regulated output, the remaining poles and zeros for the compensator are located at: from (equation 26), it can be seen that the control to output transfer function fr equency dependence is a function of the output load resistance, the value of output capacitor and inductor, and the output capacitance esr. these variations must be considered when compensating the control loop. the worst case small signal operating poin t for a voltage mode converter tends to be at maximum vin, maximum load, maximum c out , and minimum esr. the higher the desired bandwidt h of the converter, the more difficult it is to create a solution that is stable over the entire operating range. a good rule of th umb is to limit the bandwidth to about f sw /4, where f sw is the switching frequency of the converter. however, due to the bandwidth constraints of the opto- coupler and the lm431 shunt regulator, the bandwidth was reduced to about 25khz. the first pole is placed at the origin by default (c20 is an integrating capacitor). if the two zeroes are placed at the same frequency, they should be placed at f lc /2, where f lc is the resonant frequency of the output l-c filter. to reduce the gain peaking at the l-c resonant frequency, the two zeroes are often separated. when they are separated, the first zero may be placed at f lc /5, and the second at just above f lc . the second pole is placed at the lowest expected zero cause by the output capacitor esr. the third, and last pole is placed at about 1.5 times the cross over frequency. some liberties where taken with the generally accepted compensation procedure described above due to the transfer characteristics of the opto coupler. the effects of the opto- coupler tend to dominate over those of the lm431 so the gbwp effects of the lm431 are not included here. the gain and phase characteristics of the opto coupler are shown in figure 22a. figure 21a. control-to-output gain 10 100 1?10 6 -20 -10 0 10 20 30 40 frequency (hz) gain (db) 1?10 5 1?10 4 1?10 3 figure 21b. control-to-output phase 10 100 1?10 6 -200 -150 -100 -50 0 50 frequency (hz) phase (degrees) 1?10 5 1?10 4 1?10 3 f p2 1 2 r21 c20 ? ? ---------------------------------------- - = (eq. 27) f p3 1 2 r4 ? c22 ? ------------------------------------- c19 c20 ? (eq. 28) f z1 1 2 r21 ? c19 ? ---------------------------------------- - = (eq. 29) f z2 1 2 r23 ? c22 ? ---------------------------------------- - r23 r4 ? (eq. 30) figure 22a. opto coupler gain -20 -15 -10 -5 0 5 10 frequency (hz) gain (db) 10 100 1?10 6 1?10 5 1?10 4 1?10 3 figure 22b. opto coupler -90 -45 0 45 90 frequency (hz) phase (degrees) 10 100 1?10 6 1?10 5 1?10 4 1?10 3
isl6740, ISL6741 24 fn9111.6 december 2, 2011 the following compensation components were selected r 23 = 9.53k r 24 = 2.49k r 4 = 499 r 21 = 4.22k c 22 = 1nf c 20 = 82pf c 19 = 0.22 f from (equations 27, 28, 29 and 30), the poles and zeroes are: f z1 = 171hz f z2 = 16.7khz f p2 = 460khz f p3 = 319khz the calculated gain and phase plot s of the error amplifier appear below using an ideal op amp. the gain and phase plots combined with the opto coupler?s transfer characteristics appe ar in figures 24a and 24b: using the control-to-output transfer function combined with the ea transfer function, the loop gain and phase may be predicted. the predicted loop gain and phase margin of the converter appear in figures 25a and 25b: figure 23a. ideal error amplifier gain -10 0 10 20 frequency (hz) gain (db) 10 100 1?10 6 1?10 5 1?10 4 1?10 3 figure 23b. ideal error amplifier phase -90 -45 0 45 90 frequency (hz) phase () 10 100 1?10 6 1?10 5 1?10 4 1?10 3 figure 24a. ea plus opto coupler gain -10 0 10 20 30 frequency (hz) gain (db) 10 100 1?10 6 1?10 5 1?10 4 1?10 3 figure 24b. ea plus opto coupler gain -180 -135 -90 -45 0 45 90 frequency (hz) phase (degrees) 10 100 1?10 6 1?10 5 1?10 4 1?10 3 figure 25a. predicted loop gain -50 -40 -30 -20 -10 0 10 20 30 40 50 frequency (hz) gain (db) 100 1?10 5 1?10 4 1?10 3
isl6740, ISL6741 25 fn9111.6 december 2, 2011 the actual loop gain and phase margin measured on the isl6740eval2z demonstration board appear in figures 26a and 26b: the only major discrepancies between the predicted behavior and the measured results are the q of the l-c filter and the phase behavior above 60khz. the actual q appears to be significantly less than predicted resulting in less gain peaking and a less rapid phase shift near the resonant frequency. this is most likely the result of neglecting other losses in the converter?s output, such as the fet on resistance, copper losses, and inductor resistance. the phase discrepancy above 60khz is not particularly relevant to the loop performance since it occurs well above the cross over frequency. the predicted behavior indicates a much gentler drop off of phase than was observed in the measured performance. the discrepancy was not investigated. performance the major performance criteria for the converter are efficiency and load regulation. these quantities are detailed in figures 27 and 28. the efficiency, although very good, could be further improved using a controlled sr method instead of using a self-driven method with an auxiliary scho ttky diode. the schottky diode conducts when the main switching fets are off. its forward voltage drop is considerably larger than that of the sr fets and causes a measurable reduction in efficiency. the effect becomes more significant as the input voltage is increased due to the reduction of duty cycle (and consequent increase in the off time). figure 25b. predicted loop phase margin -135 -90 -45 0 45 90 135 180 225 frequency (hz) phase margin () 100 1?10 5 1?10 4 1?10 3 figure 26a. measured loop gain 0.1k 1k 10k 100k -50 -40 -30 -20 -10 0 10 20 30 40 50 frequency (hz) gain (db) figure 26b. measure loop phase margin 0.1k 1k 10k 100k -135 -90 -45 0 45 90 135 180 225 frequency (hz) phase margin () figure 27. efficiency vs load v in = 48v t 2345678910 85 87 89 91 93 95 load current (a) efficiency (%) figure 28. load regulation at v in = 48v 012345678910 11.995 12.000 12.005 12.010 12.015 load current (a) output voltage (v)
isl6740, ISL6741 26 fn9111.6 december 2, 2011 references [1] dixon, lloyd h., ?closing the feedback loop?, unitrode power supply design seminar, sem-700, 1990. component list reference designator value description c 1 1.0 f capacitor, 1812, x7r, 100v, 20% tdk c4532x7r2a105m c 2 , c 3 3.3 f capacitor, 1812, x5r, 50v, 20% tdk c4532x5r1h335m c 4 , c 6 1.0 f capacitor, 0805, x5r, 16v, 10% tdk c2012x5r1c105k c 5 , c 15 , c 16 0.1 f capacitor, 0603, x7r, 50v, 10% tdk c1608x7r1h104k c7 open capacitor, 0603, open c 8 , c 21 22 f capacitor, 1812, x5r, 16v, 20% tdk c4532x5r1c226m c 9 150 f capacitor, radial, sanyo 16sh150m c 10 , c 14 , c 22 1000pf capacitor, 0603, x7r, 50v, 10% tdk c1608x7r1h102k c 11 , c 12 560 pf capacitor, 0603, x7r, 100v, 10% tdk c1608x7r2a561k c 13 220pf capacitor, 0603, x7r, 100v, 10% tdk c1608x7r2a221k c 17 220pf capacitor, 0603, cog, 16v, 5% tdk c1608cog1c221j c 18 0.047 f capacitor, 0603, x7r, 16v, 10% tdk c1608x7r1c473k c 19 0.22 f capacitor, 0603, x7r, 16v, 10% tdk c1608x7r1c224k c 20 82pf capacitor, 0603, x7r, 16v, 10% tdk c1608x7r1c820k c r1 , c r2 diode, schottky, bat54s c r3 , c r5 , c r6 diode, schottky, bat54 c r4 diode, schottky, ir 12cwq06fnpbf d 1 zener, 10v, philips bzx84-c10 d 2 zener, 6.8v, philips bzx84-c6v8 l 1 190nh pulse, p2004nl l 2 4.0 h bi technologies, hm65-h4r0lf l 3 short 0 ohm jumper q 5 transistor, onsemi mjd31cg q l , q h , q r1 , q r2 , q r3 , q r4 fet, fairchild fds3672 r 1 3.3 resistor, 2512, 5% r 2 3.01k resistor, 2512, 2% r 3 10.0 resistor, 0603, 1% r 4 , r 25 499 resistor, 0603, 1% r 5 2.20 resistor, 0805, 1% r 6 200 resistor, 0603, 1% r 7 75.0k resistor, 0805, 1% r 8 , r 9 , r 10 18 resistor, 2512, 5% r 11 205 resistor, 0603, 1% r 12 8.06k resistor, 0603, 1% r 13 18.2k resistor, 0603, 1% r 14 open resistor, 0603, open r 15 1.27k resistor, 0603, 1% r 16 , r 19 1.00k resistor, 0603, 1% r 17 97.6k resistor, 0603, 1% r 18 3.01k resistor, 0603, 1% r 20 2.00k resistor, 0603, 1% r 21 4.22k resistor, 0603, 1% r 23 9.53k resistor, 0603, 1% r 24 2.49k resistor, 0603, 1% r 26 , r 27 5.11 resistor, 0805, 1% r t1 10.0k resistor, 0603, 1% t 1 midcom 31660-lf1 t 2 pulse p8205nl u 1 intersil hip2101ibz u 2 nec ps2801-1-a u 3 isl6740ibz u 4 national lm431bim3/nopb component list (continued) reference designator value description
isl6740, ISL6741 27 fn9111.6 december 2, 2011 package outline drawing m16.173 16 lead thin shrink small outline package (tssop) rev 2, 5/10 0.09-0.20 see detail "x" detail "x" typical recommended land pattern top view side view end view dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 per side. dimension does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 per side. dimensions are measured at datum plane h. dimensioning and tolerancing per asme y14.5m-1994. dimension does not include dambar protrusion. allowable protrusion shall be 0.08mm total in excess of dimension at maximum material condition. minimum space between protrusion and adjacent lead is 0.07mm. dimension in ( ) are for reference only. conforms to jedec mo-153. 6. 3. 5. 4. 2. 1. notes: 7. (0.65 typ) (5.65) (0.35 typ) 0.90 +0.15/-0.10 0.60 0.15 0.15 max 0.05 min plane gauge 0-8 0.25 1.00 ref (1.45) 16 2 1 3 8 b 1 3 9 a pin #1 i.d. mark 5.00 0.10 6.40 4.40 0.10 0.65 1.20 max seating plane 0.25 +0.05/-0.06 5 c h 0.20 c b a 0.10 c - 0.05 0.10 c b a m
isl6740, ISL6741 28 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn9111.6 december 2, 2011 for additional products, see www.intersil.com/product_tree small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of pub- lication number 95. 2. dimensioning and tole rancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interl ead flash or protrusions. interlead flash and protrusions shall not exc eed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index fea- ture must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m m16.15 (jedec ms-012-ac issue c) 16 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.3859 0.3937 9.80 10.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n16 167 0 8 0 8 - rev. 1 6/05

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